SKY130 · Serial Transceiver · Tiny Tapeout

Single-Lane
SerDes PHY

240 Mbps Manchester-encoded differential transceiver on the SKY130 open-source node. Integrated PLL, CDR, dual FIFOs, and PRBS-7 self-test.

240 Mbps Manchester CDR Ring-Osc PLL · 10× Bang-Bang CDR I²C Config PRBS-7 Analog Loopback

240Mbps

Line Rate

24MHz

Ref Clock

1.8V

Digital VDD

8

CSR Regs

Device Overview

What Is the SKY130 SerDes PHY?

Single-lane differential transceiver at 240 Mbps using a 100 Ω differential CML I/O pair (TXP/TXN, RXP/RXN).
Manchester line coding for DC balance and embedded clock — every bit contains a guaranteed transition, enabling clock recovery without a separate clock signal.
Ring-oscillator PLL multiplies the 24 MHz reference by 10× to generate the 240 MHz TX serializer clock. Lock time ≈ 8 µs.
Bang-bang CDR (Alexander architecture) recovers clock from the incoming data stream. Acquisition range ±2000 ppm, lock time ≤ 100 µs.
Dual 8-word FIFOs (TX and RX) with 4-bit external interface bridge the 24 MHz control domain and 240 MHz serial domain.
PRBS-7 generator and checker enable loopback self-test without external equipment. Configured via 8 I²C registers at address 0x42.

Applications

FPGA / ASIC prototyping links
Multi-chip module serial buses
Educational SerDes demonstration
Tiny Tapeout SoC integration

Supply

DVDD: 1.8 V
AVDD: 3.3 V
Active: ~12 mA
Idle: <200 µA

System Architecture

PCS + PMA Hierarchy

serdesphy_top

Top-Level Integrator + Clock Distribution

tt_um_raybello_serdesphy_top

Tiny Tapeout IO Wrapper (ui_in / uo_out / uio)

PCS — Digital

TX Top

FIFO·MUX·Codec

RX Top

Codec·FIFO·Align

CSR Top (I²C Slave + Registers)

Addrs 0x00–0x07

PMA — Analog

TX Diff Driver

CML 100Ω

PLL · 24→240 MHz

PFD·CP·LPF·VCO÷10

CDR · Bang-Bang

Alexander PD·VCO

RX Diff Receiver

Limiting Amp

PCS ↔ PMA Interface

Signal Group	Count
PLL control	5 sig
CDR control	3 sig
TX serializer ctrl/status	7 sig
RX deserializer ctrl/status	7 sig
Clock outputs	clk_240m_tx, _rx

clk_240m_tx ← PLL VCO
clk_240m_rx ← CDR VCO
Independent recovered clock

Clock Architecture

Three Independent Clock Domains

CLK_24M — Reference Domain

All CSRs, FIFO control, word assembler/disassembler, Manchester codec, PRBS gen/check, POR logic.

CLK_240M_TX — Transmit Domain

Serializer shift register, TX differential driver. Source: PLL VCO output.

CLK_240M_RX — Receive Domain

Deserializer shift register, RX data capture. Source: CDR VCO (recovered from data).

PLL Specifications

Parameter	Typ	Unit
Input frequency	24.0	MHz
Output frequency	240	MHz
Multiply ratio	10×	—
Lock time	~8	µs
Jitter (RMS)	50	ps
VCO tuning range	200–400	MHz

CDC Mechanisms

• Dual-flop reset sync (reset_synchronizer)
• Gray-code pointer FIFOs (TX + RX)
• No combinatorial CDC paths

Transmit Datapath

4-bit Parallel → 240 Mbps Serial

01

Word
Assembler

4b→8b

→

02

TX FIFO

8×8b deep

→

03

Data MUX

FIFO/PRBS

→

04

Manchester
Encoder

8b→16b

→

05

Serializer

240 MHz

→

06

CML Driver

TXP/TXN

Stage Details

Word Assembler: Two consecutive 4-bit nibbles (CLK_24M) → 8-bit word. FSM: WAIT_N0 → WAIT_N1 → READY.
TX FIFO: 8-entry × 8-bit, single clock domain. Full threshold: 7. Overflow → FIFO_ERR (sticky).
Data MUX: Selects FIFO output or PRBS-7 generator. TX_IDLE overrides both (all zeros).
Serializer: 16-bit shift register clocked at 240 MHz (15 ns/bit). One 8-bit word → 16 serial bits @ 4.17 ns/symbol.

TX FIFO Parameters

Parameter	Value
Depth	8 words
Internal width	8 bits
External width	4 bits
Write clock	24 MHz
Effective write rate	12 MHz (gated)
Overflow action	FIFO_ERR + discard

Line Coding

Manchester Encoding

Encoding Rules

Logic 0 → High-to-Low transition at bit center (symbol: 10)
Logic 1 → Low-to-High transition at bit center (symbol: 01)
Every bit contains exactly one transition — clock embedded in data
Symbol rate doubles: 1 bit → 2 symbols at 240 Mbaud

Encoding Properties

Property	Value
DC balance	±0 over any 2 symbols
Transition density	100%
Max run length	1 symbol
Symbol rate	240 Mbaud
Bit rate	120 Mbps effective

Waveform Example

// Data: 1    0    1    1    0
// Symbol:  01  10  01  01  10

DATA: ‾‾‾|___|‾‾‾|‾‾‾|___|
TX  : _‾|‾_|_‾|_‾|‾_|
         ↑   ↑   ↑   ↑   ↑
         mid-bit transitions
        

Why Manchester?

DC-free signalling avoids transformer saturation and AC-coupled link baseline wander. Guaranteed transitions enable the bang-bang CDR to lock without a preamble or training sequence.

Receive Datapath

240 Mbps Serial → 4-bit Parallel

01

Diff RX

~10 mV sens.

→

02

CDR
Phase Det.

Bang-Bang

→

03

Deserializer

16-bit SR

→

04

Manchester
Decoder

16b→8b

→

05

RX FIFO

CDC 240→24M

→

06

Word
Disassem.

8b→4b

Stage Details

Diff RX: Limiting amplifier with ≈10 mV sensitivity. Supports analog loopback (LPBK_EN).
Deserializer: 16-bit shift register clocked by recovered 240 MHz CDR clock. Outputs 16-bit word per 16 cycles.
Manchester Decoder: Validates biphase symbols; raises error flag on invalid patterns. 16b → 8b decoded data.
RX FIFO: Dual-clock FIFO bridges 240 MHz RX domain → 24 MHz core domain. Overflow/underflow → FIFO_ERR.
Word Disassembler: 8b word → two sequential 4-bit nibbles on RXD[3:0]. RX_VALID strobes each nibble.

Alignment FSM

IDLE

→

SEARCH

→

ALIGNED

CDR Specifications

Acq range: ±2000 ppm
Lock time: ≤100 µs
Bandwidth: ~1 MHz
Phase err: <10 UI RMS

Clock Data Recovery

Alexander Bang-Bang CDR

Architecture

The Alexander (bang-bang) phase detector samples the incoming data at three points: early, on-time, and late. Comparing early vs. late samples determines whether the recovered clock leads or lags the data transitions.

Phase error: Binary — only magnitude of 1 step per update. No linear phase error term.
Loop gain set by CDR_GAIN[2:0] register (0x3–0x6 recommended). Higher gain → wider bandwidth, less noise immunity.
Fast lock mode (CDR_FAST_LOCK=1): Doubles loop gain during acquisition. Lock detection threshold halved from 1200 to 600 cycles.
CDR VCO tracks ±2000 ppm around 240 MHz. Control word is 8-bit digital.

CDR FSM

RESET

→

ACQUIRE

→

TRACK

→

LOCKED

CDR Config Register (0x05)

Bits	Name	Description
[2:0]	CDR_GAIN	Loop gain (0x4 default)
[3]	CDR_FAST_LOCK	2× gain in acquisition
[4]	CDR_RST	Active-high reset

Lock Condition

CDR_LOCK asserts when phase error < 0.1 UI for > 64 consecutive recovered bits. Exposed on STATUS[1] and OUT5 pin.

Tracking

Once locked, tracking bandwidth ≈ 1 MHz. The bang-bang nature introduces limit-cycle jitter — mitigate by reducing CDR_GAIN when lock is stable.

Transmit PLL

Ring-Oscillator Integer-N PLL

CLK_REF

24 MHz

→

Phase/Freq Det.

PFD

Charge Pump

CP_CURRENT[1:0]

→

Loop Filter

vco_control[7:0]

Ring-Osc VCO

VCO_TRIM[3:0]

→

CLK_240M_TX

Output

÷10 Freq Divider

Feedback to PFD

RESET

→

ACQUIRE

240 cycles

→

TRACK

→

LOCKED

PLL Config Register (0x04)

Bits	Name	Description
[3:0]	VCO_TRIM	Coarse freq trim (0x8=240 MHz)
[5:4]	CP_CURRENT	Charge pump current (0x2=40 µA)
[6]	PLL_RST	Active-high reset
[7]	PLL_BYPASS	Bypass for test

VCO_TRIM Encoding

Value	VCO Freq
0x0	~200 MHz
0x8	~240 MHz (nominal)
0xF	~400 MHz

CP_CURRENT

Value	Current
0x0	10 µA
0x1	20 µA
0x2	40 µA (default)
0x3	80 µA

Clock Domain Crossing

FIFO Buffering & CDC Strategy

Three Independent Domains

24 MHz — CSR / control / codec
240 MHz TX — serializer (PLL clock)
240 MHz RX — deserializer (CDR clock)

TX FIFO (single-clock)

8-entry × 8-bit. Both ports in 24 MHz domain.
Serializer reads on empty: underflow → FIFO_ERR sticky.
Overflow action: discard write, assert FIFO_ERR.

RX FIFO (dual-clock)

Write port: 240 MHz RX domain (CDR clock).
Read port: 24 MHz domain (core clock).
Gray-code pointers prevent metastability on full/empty flags.

Reset Synchronizer

// serdesphy_reset_synchronizer
// Dual-flop per domain

rst_n_24m     ← rst_n_in   (24M)
rst_n_240m_tx ← pll_rst    (TX)
rst_n_240m_rx ← cdr_rst    (RX)

// Sequential release order:
1. assert RST_N_IN
2. release PLL reset → wait PLL_LOCK
3. release CDR reset → wait CDR_LOCK
        

CDC Rules

No combinatorial CDC paths. All control signals cross via dual-flop synchronizers. Data crosses only through gray-coded FIFOs. Status sticky bits (PRBS_ERR, FIFO_ERR) clear on register read.

Built-In Self-Test

PRBS-7 Generator & Checker

Generator (TX Side)

// LFSR polynomial: x⁷ + x⁶ + 1
feedback = lfsr[6] ^ lfsr[5];
lfsr <<= 1;
lfsr[0] = feedback;

// Output: 8-bit parallel @ 24 MHz
// Initial state: 0x7F (all ones)
// Bypasses TX FIFO when enabled
        

Checker (RX Side)

Maintains local LFSR, compares with decoded 8-bit words.
Single-bit error detection per 8-bit word.
Error counter: 8-bit, saturates at 255. Reset via RX_ALIGN_RST.
PRBS_ERR flag: sticky, clears on STATUS register read.

Self-Test Procedure

Enable PHY: PHY_EN=1, wait PLL_LOCK.
Enable TX PRBS: TX_PRBS_EN=1, TX_EN=1.
Set TX data select: TX_DATA_SEL=0 (PRBS source).
Release CDR reset, wait CDR_LOCK on STATUS[1].
Enable RX checker: RX_PRBS_CHK_EN=1, RX_EN=1.
Monitor STATUS[6] (PRBS_ERR) — should stay low.
Inject error (loopback off) → verify PRBS_ERR asserts.

Loopback Path

Set LPBK_EN=1 to route TXP/TXN internally to RXP/RXN through the analog loopback switch. Full end-to-end test without external cabling.

Configuration Interface

I²C Register Map — Addr 0x42

0x00

PHY_ENABLE

PHY_EN [0], ISO_EN [1]. Global power gate + analog isolation.

0x01

TX_CONFIG

TX_EN, TX_FIFO_EN, TX_PRBS_EN, TX_IDLE. Controls TX data source selection.

0x02

RX_CONFIG

RX_EN, RX_FIFO_EN, RX_PRBS_CHK_EN, RX_ALIGN_RST (self-clearing).

0x03

DATA_SELECT

TX_DATA_SEL [0]: 0=PRBS, 1=FIFO. RX_DATA_SEL [1]: 0=FIFO, 1=PRBS status.

0x04

PLL_CONFIG

VCO_TRIM[3:0], CP_CURRENT[1:0], PLL_RST[6], PLL_BYPASS[7].

0x05

CDR_CONFIG

CDR_GAIN[2:0], CDR_FAST_LOCK[3], CDR_RST[4]. Gain range: 0x3–0x6 recommended.

0x06 R/O

STATUS

PLL_LOCK, CDR_LOCK, TX/RX FIFO full/empty, PRBS_ERR, FIFO_ERR. Sticky bits clear on read.

0x07

DEBUG_ENABLE

DBG_VCTRL, DBG_PD, DBG_FIFO. Routes one analog signal to DBG_ANA pin. One source at a time only.

// I²C Write format:
START | 0x42+W | ACK | REG_ADDR | ACK | DATA | ACK | STOP
// I²C Read format:
START | 0x42+W | ACK | REG_ADDR | ACK | Rstart | 0x42+R | ACK | DATA | NACK | STOP
      

Power Management

Power-On Reset Sequence

POR FSM States

RESET

All held in reset

↓

WAIT_SUPPLY

Debounce ~2 µs

↓

SEQUENCING

Release isolation → digital → analog

↓

READY

Normal operation + supply monitoring

Supply Inputs

DVDD_OK: 1.8 V digital supply stable.
AVDD_OK: 3.3 V analog supply stable.
Both must be asserted before SEQUENCING begins.
Supply loss mid-operation → RESET state.

Output Signals

Signal	Role
POWER_GOOD	All supplies OK
ANALOG_ISO_N	De-asserts bias disconnect
DIGITAL_RESET_N	Digital core reset
ANALOG_RESET_N	PLL / CDR reset
POR_ACTIVE	POR in progress
POR_COMPLETE	Sequencing done

Sequencing Rule

ISO_EN must de-assert before digital reset. Prevents inrush into unpowered analog bias circuits. PHY_EN must be 0 until POR_COMPLETE.

Typical Application

Loopback Self-Test Configuration

Initialization Sequence

Apply AVDD, then DVDD. Supply sequencing required.
Assert RST_N low for ≥10 CLK_REF cycles.
Write 0x01 → PHY_ENABLE (PHY_EN=1)
Write 0x00 → PLL_CONFIG[6] (release PLL reset)
Poll STATUS[0] until PLL_LOCK asserts. ~8 µs
Write 0x05 → TX_CONFIG (TX_EN + TX_PRBS_EN)
Write 0x00 → DATA_SELECT (PRBS source)
Write 0x00 → CDR_CONFIG[4] (release CDR reset)
Write 0x05 → RX_CONFIG (RX_EN + RX_PRBS_CHK_EN)
Poll STATUS[1] until CDR_LOCK asserts. ≤100 µs
Monitor STATUS[6] — PRBS_ERR should remain low.

Register Write Summary

Step	Reg	Value
3	0x00	0x01
4	0x04	0x28 (PLL_RST=0)
6	0x01	0x05 (TX_EN+PRBS_EN)
7	0x03	0x00 (PRBS src)
8	0x05	0x04 (CDR_RST=0)
9	0x02	0x05 (RX_EN+CHK_EN)

Loopback Enable

Set LPBK_EN (IO6 pin) high to connect TXP/TXN → RXP/RXN through the analog loopback switch before step 8. Allows full datapath test without external loopback fixture.

Package Interface

24-Pin QFN Assignment

Inputs (IN0–IN7)

Pin	Symbol	Description
IN0	CLK_REF	24 MHz ref, 50% duty CMOS
IN1	RST_N	Active-low async reset
IN2–5	TXD[3:0]	4-bit TX data (CMOS)
IN6	TX_VALID	TX data valid strobe
IN7	TEST_MODE	Test mode enable

Outputs (OUT0–OUT7)

Pin	Symbol	Description
OUT0–3	RXD[3:0]	4-bit RX data (CMOS)
OUT4	PLL_LOCK	PLL frequency lock
OUT5	CDR_LOCK	CDR phase lock
OUT6	PRBS_ERR	PRBS error (latched)
OUT7	RX_VALID	RX data valid strobe

Bidirectional (IO0–IO7)

Pin	Symbol	Description
IO0	SDA	I²C data (open-drain)
IO1	SCL	I²C clock ≤24 MHz
IO2	TXP	TX diff (+) CML 100Ω
IO3	TXN	TX diff (−) CML 100Ω
IO4	RXP	RX diff (+) CML 100Ω
IO5	RXN	RX diff (−) CML 100Ω
IO6	LPBK_EN	Analog loopback enable
IO7	DBG_ANA	Analog debug output

Package

24-pin QFN · 4×4 mm · 0.5 mm pitch
Exposed pad: 2.5×2.5 mm (GND)
P/N: SKY130-SERDES-240M
Temp: −40°C to +85°C

Electrical Characteristics

DC Parameters & Operating Conditions

Recommended Operating Conditions

Parameter	Min	Typ	Max	Unit
DVDD	1.71	1.8	1.89	V
AVDD	3.0	3.3	3.6	V
T_A	−40	25	85	°C
CLK_REF	23.5	24.0	24.5	MHz

Absolute Maximum Ratings

Parameter	Min	Max
DVDD	−0.3	2.0 V
AVDD	−0.3	3.6 V
Digital input	−0.3	DVDD+0.3
Diff input (RXP/N)	−0.5	AVDD+0.5

DC Characteristics

Parameter	Min	Typ	Unit
V_IH (digital)	0.7×DVDD	—	V
V_IL (digital)	—	0.3×DVDD	V
Diff input sens.	10	—	mV_pp
Diff output swing	400	600	mV_pp
I_DD active	—	12	mA
I_DD idle	—	100	µA

I²C Timing

f_SCL max: 24 MHz
t_LOW/HIGH min: 0.5 µs
SDA setup: 100 ns
SDA hold: 0 ns

Tiny Tapeout Integration

tt_um_raybello_serdesphy_top Wrapper

IO Mapping

TT Signal	SerDes Pin
ui_in[0]	CLK_REF (24 MHz)
ui_in[1]	RST_N
ui_in[5:2]	TXD[3:0]
ui_in[6]	TX_VALID
ui_in[7]	TEST_MODE
uo_out[3:0]	RXD[3:0]
uo_out[4]	PLL_LOCK
uo_out[5]	CDR_LOCK
uo_out[6]	PRBS_ERR
uo_out[7]	RX_VALID

Bidirectional IO Mapping

TT Signal	SerDes Pin
uio[0]	SDA (I²C)
uio[1]	SCL (I²C)
uio[2]	TXP
uio[3]	TXN
uio[4]	RXP
uio[5]	RXN
uio[6]	LPBK_EN
uio[7]	DBG_ANA

// project.v wrapper pattern
assign clk_ref_24m = ui_in[0];
assign rst_n       = ui_in[1];
assign tx_data     = ui_in[5:2];
assign uo_out[4]  = pll_lock;
        

Design Summary

SKY130 SerDes PHY — What We Built

240 Mbps single-lane transceiver on the open-source SKY130 process node. Manchester encoding provides DC balance and embedded clock recovery.
Integrated transmit PLL: ring-oscillator VCO with 10× multiplication (24→240 MHz), charge-pump architecture, configurable VCO trim and CP current via I²C.
Bang-bang CDR (Alexander architecture) with ±2000 ppm acquisition range and configurable loop gain for bandwidth/noise trade-off.
PRBS-7 self-test engine (generator + checker) enables bit-error measurement without external equipment, using analog loopback path.
Full I²C control at 0x42: 8 registers covering enable, TX/RX config, PLL/CDR tuning, status, and debug signal routing.
Tiny Tapeout compatible: all 24 SerDes signals mapped to ui_in/uo_out/uio with a thin wrapper in project.v.

Design Metrics

Modules: ~44 Verilog files
Domains: 3 (24M, 240M TX, 240M RX)
CSR: 8 registers × 8 bits
FIFOs: 2 × 8-entry dual-clock
Loopback: Analog + digital paths

Revision

v0.0.1 · December 2025 · Ray Bello
Part: SKY130-SERDES-240M
24-pin QFN · −40°C to +85°C

SKY130 Open Source PDK Tiny Tapeout v0.0.1

Single-LaneSerDes PHY

What Is the SKY130 SerDes PHY?

PCS + PMA Hierarchy

PCS ↔ PMA Interface

Three Independent Clock Domains

PLL Specifications

4-bit Parallel → 240 Mbps Serial

Stage Details

TX FIFO Parameters

Manchester Encoding

Encoding Rules

Encoding Properties

Waveform Example

240 Mbps Serial → 4-bit Parallel

Stage Details

Alignment FSM

Alexander Bang-Bang CDR

Architecture

CDR FSM

CDR Config Register (0x05)

Ring-Oscillator Integer-N PLL

PLL Config Register (0x04)

VCO_TRIM Encoding

CP_CURRENT

FIFO Buffering & CDC Strategy

Three Independent Domains

TX FIFO (single-clock)

RX FIFO (dual-clock)

Reset Synchronizer

PRBS-7 Generator & Checker

Generator (TX Side)

Checker (RX Side)

Self-Test Procedure

I²C Register Map — Addr 0x42

Power-On Reset Sequence

POR FSM States

Output Signals

Loopback Self-Test Configuration

Initialization Sequence

Register Write Summary

24-Pin QFN Assignment

Inputs (IN0–IN7)

Outputs (OUT0–OUT7)

Bidirectional (IO0–IO7)

DC Parameters & Operating Conditions

Recommended Operating Conditions

Absolute Maximum Ratings

DC Characteristics

tt_um_raybello_serdesphy_top Wrapper

IO Mapping

Bidirectional IO Mapping

SKY130 SerDes PHY — What We Built

Single-Lane
SerDes PHY